PRIORITY INTERRUPT

WHAT IS IT?

IT IS A SYSTEM THAT DETERMINES,WHICH DEVICE TO BE SERVICED FIRST WHEN TWO OR MORE REQUESTS ARRIVE SIMULTANEOUSLY.HIGHEST PRIORITY INTERRUPTS ARE SERVICED FIRST.DEVICE WITH HIGH SPEED TRANSFERS ARE GIVEN HIGH PRIORITY AND SLOW DEVICES SUCH AS KEYBOARD RECEIVE LOW PRIORITY. WHEN TWO DEVICES INTERRUPT THE COMPUTER AT THE SAME TIME ,THE COMPUTER SERVICES THE DEVICE WITH THE HIGHER PRIORITY FIRST.

TASKS TO BE PERFORMED:

• Identify the source(s) of the interrupt(s) – There may be several simultaneous interrupts.
• Prioritize interrupts to select the device requiring service first
• Service the selected interrupt

PRIORITIZING INTERRUPTS

Software: A polling procedure is used to identify the interrupt source having the highest priority. Only one branch address is used for all interrupts. The priority of each interrupt source determines the order in which it is polled. The source with the highest priority is tested first, and if its interrupt signal is on, control branches to a routine that services that source. Otherwise, the source with the next lower priority is tested, and so on.

Hardware: A hardware priority interrupt unit functions as an overall manager in an interrupt system environment. The unit accepts interrupt requests from many sources, determines which request has the highest priority, and issues an interrupt request to the computer based on this determination.

TO SPEED UP THE OPERATION, EACH INTERRUPT SOURCE HAS ITS OWN INTERRUPT VECTOR ADDRESS TO ACCESS ITS OWN SERVICE ROUTINE DIRECTLY.

DAISY CHAIN PRIORITY INTERRUPT CONTD.

• All devices that can request an interrupt are connected serially and in priority order with the highest priority device placed first on the daisy chain, farthest from the CPU, and the lowest priority device placed last and closest to the CPU.
• First, any (or all) of the devices signal an interrupt on the Interrupt Request line.
• Next, the CPU acknowledges the interrupt on the Interrupt Acknowledge line.
• A device on the line passes the Interrupt Acknowledge signal to the next lower priority device only if it has NOT requested service.
• The first device on the priority chain requiring service asserts it interrupt vector address (VAD) on the CPU data bus.

A device with a 0 on its PI input generates a 0 on its P0 output to inform the device with the next lower priority that the acknowledge signal has been blocked.

A device that is requesting an interrupt and has a 1 on its PI input will intercept the acknowledge signal by placing a 0 on its PO output.

If the device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 on its PO output.

Thus, the device with PI=1 and PO=0 is the one with the highest priority that is requesting an interrupt, and this device places its VAD on the data bus.

PARALLEL PRIORITY INTERRUPT

The parallel priority interrupt method employs two registers to manage interrupted.

The Interrupt Register is used to record which devices require service. Devices are prioritized by the position of the bits in the register used to record a request for service. Bit position 3 identifies the device having the highest priority and bit position 0 is set by the device having the lowest priority.

The mask register can be programmed to disable lower priority devices while a higher priority device is being serviced. Service for a lower priority device may be interrupted to serve a higher priority device by employing the mask register.

The Priority Encoder produces two outputs, signal V and the least significant two bits of the VAD. Signal V is asserted when service is requested. The least significant two bits of the VAD designate the location of the service routine associated with the device making the request.

PRESENTED TO YOU BY

Shashank Sharma
01616403211
fifth semester
B.Tech CSE
USICT